Ws2126 VME Board
Ws2126 VME Board

The WS2126 VME SHARC cluster is a fast 6 HE, 3 TE VME master/slave board with 6 ADSP 2106x. The WS2126 was specially designed for embedded and OEM applications. The VME board uses the new Analog Device ADSP-2106x SHARC Signal Processor. Up to six onboard SHARC DSPs can perform a peak rate of 720 MFLOPs. The board has a VME compliant Master/Slave interface. In master mode the WS2126 can be the owner of VME resources.

The VME board is a complete SHARC cluster and was designed in a way, that an application can easily be adapped to such cluster hardware, of course with our well known high functionality. Wiese Signalverarbeitung uses an open interface called the SHARC IO-Pack. This interface is easy to handle but provides the user with the full SHARC functionality. Each SHARC can be augmented with its own mezzanine board, with the possibility to use the SHARC -LINK, -SIO, -IRQ and -FLAG lines. Also memory mapped SHARC Devices (if you want with DMA facilities) can be utilized with no or a little overhead.

The WS2126 confirms to the VME Specification. The board can hold up to 3 MByte static RAM and all the necessities used to debug the board with the EZ-ICE Debugger from Analog Devices.

All local bus devices are transparent to both the SHARCs and the VME host, e.g. SHARC internal register and memory spaces are transparent to the VME host. The same mechanism is used for the SHARC IO-Pack. The WS2126 itself can be mapped to any portion of the 4 Gbyte VME address space. Multiply WS2126 boards can be used in parallel.

Wiese Signalverarbeitung supports the WS2126 with a sophisticated object oriented class library, the WS2126-DDL. This device driver library (DDL) was available as a linkable object library, or as a callable device driver) enables one to program the SHARCs directly, without worrying about petty IO-handling details. The DDL supports both master and slave functionality and is available for DOS, Windows and Windows NT applications. Applications with more than one board will supported by the DDL too.

Key Benefits

  • Six SHARC ADSP 21060 or ADSP 21062 share one local multiprocessor bus
  • Up to 512K * 48 bit static on board multiprocessor memory, accessible for DSP and the VME bus
  • VME A32/D16 and D32 host interface to the multiprocessor DSP bus.
  • Each DSP can act as a VME master
  • A local D16 bus leads to a configuration-/ FIFO window multiprocessor bus.
  • FIFO is connected between the DSP bus and the local bus to support VME bus readout without intervention of the DSP bus.
  • FIFO size can be choosen from 2K to 32K * 16 Bit.
  • Programable VME IRQ level. Each DSP can request an interrupt on the VME bus.
  • All links of all DSPs are routable to the front end connectors (6 links for every DSP).
  • Three on board link busses to increase the interprocessor communication paths
  • Possible and mixed configurations are piped, point-to-point and bussed
  • Customized logic for each DSP over an dedicated slot for one SHARC IO-Pack submodule.
  • DSP bus expansion connectors to VME P2 rows a + c
  • Local bus expansion connectors to VME P2 rows a + c
  • For software debugging a JTAG connector is implemented. The EZ-ICE debugger from ADI can be connected.